CELUS Brings AI Agents to Architecture and Component Decisions in Electronics Design
October 29, 2026
The Design Assistant now drafts a plan for the engineer to approve before it does the work, and cites a source for each component it recommends
CELUS launched an agentic workflow for its Design Assistant on October 29, 2026. The workflow helps hardware engineers plan the architecture and component work at the start of an electronics design, before schematic capture, and carries out that plan once the engineer approves it. It is available now in beta on the CELUS Design Platform.
Previously, engineers starting a new system would piece together an architecture from datasheets, distributor searches and general-purpose chatbots, which can invent part numbers and leave every answer to be checked by hand against a datasheet. Until now, the Design Assistant also worked one prompt at a time, with the engineer holding the overall plan. With the agentic workflow, the assistant handles the planning and research, and the engineer makes the decisions. Engineers go through fewer revision rounds and run into fewer problems late in a project. The trade-off is that each request takes longer than a single prompt, since the assistant plans and checks its work first. The workflow:
- Captures intent: The engineer describes the product, and the assistant asks about interfaces, power budget, cost and compliance, then records the answers in an Intent Document with a step-by-step plan.
- Waits for approval: Nothing runs until the engineer approves the plan, and the engineer can stop, redirect or edit the work at any step.
- Builds the architecture: The assistant produces a block diagram of the system and researches components, citing the datasheet or specification behind each recommendation.
- Reviews its own output: It proposes fixes for errors the project reports and compares the design against the requirements in the Intent Document, flagging any it does not meet.
- Finds alternatives: When a part is expensive or has a long lead time, it ranks substitutes by price, lead time or preferred suppliers.
- Works with existing tools: Block diagrams, reference schematics and bills of materials export to Altium Designer, KiCad, Siemens EDA (Xpedition) or Autodesk Fusion.
“Engineering teams are being asked to ship more product variants on shorter schedules with fewer senior engineers, and component choices now get locked in at the very start of a project. That first stage is where we built the Design Assistant. It proposes a plan, an engineer approves it before anything goes into the design, and every recommendation links to the datasheet behind it. The decision stays with the person who has to stand behind the design,” said Tobias Pohl, founder and CEO of CELUS.
AI agents are already a standard part of software engineering, and the CELUS workflow applies them to planning physical products. More than 60,000 engineers in more than 100 countries use the CELUS platform, which draws on a library of more than 560,000 components. The Design Assistant has been in production since May 2025, and CELUS partners include NXP, Würth Elektronik and Siemens EDA. NXP offers CELUS technology to its own customers through the NXP Block Diagram Designer, Powered by CELUS.
Engineers can try the agentic workflow at app.celus.io now.
About CELUS
CELUS is an AI-powered design platform that translates engineering intent into electrically correct circuit implementations. By structuring early design exploration and connecting it to application-ready design blocks, CELUS helps engineers move faster and helps component manufacturers present solutions in real system context. CELUS is headquartered in Munich, Germany, with offices in Porto and Austin. Learn more at www.celus.io.
Related Story
CELUS Design Platform Experience Now Available on NXP.com to Accelerate System Solution Discovery and Design-In
CELUS announced that the CELUS Design Platform is now live on NXP.com in a co-branded experience featuring NXP® Semiconductors’ components and system solutions. Debuting around Embedded World North America 2026, the launch introduces a new digital path for engineers to move from high-level application intent to electrically correct schematics that embed NXP technologies in real system context.
